10th International Congress on Information and Communication Technology in concurrent with ICT Excellence Awards (ICICT 2025) will be held at London, United Kingdom | February 18 - 21 2025.
Authors - Koutaro Hachiya Abstract - As a method for testing power TSVs (Through Silicon Vias) in 3D-ICs, prior studies have proposed detecting open defects by measuring the re-sistance between power pads placed directly beneath the TSVs. However, opti-mizing the resistance measurement points and deriving the defect coverage for this test require repeated circuit simulations to calculate the resistance between power pads, which is time-consuming. To accelerate this process, this paper proposes a method to estimate defect coverage using sampling and optimize measurement points through Bayesian optimization. Numerical experiments demonstrated that the time required for defect coverage estimation was acceler-ated by a factor of 10 compared to methods without sampling. Additionally, the time needed to optimize measurement points was reduced by approximately 1.6 times compared to the conventional Exhaustive Neighborhood Search method when the approximate locations of the optimal measurement terminals were unknown.
